Certain types of non-volatile memory devices are designed so that portions of memory space must be written or erased together as a single storage unit, typically as a “page” or “block;” owing to variability in each memory cell within these designs, operations that change the cell data state (e.g. program or erase) in turn are often based on iterative cycles. These iterative cycles are called “program-verify” cycles and, despite use of “program” within this term, it should be understood that the term refers to the same basic operation whether writing or erasing of a block is performed. In each cycle, the memory device or a controller (i) attempts to change the state of the storage unit using a specific voltage, and (ii) checks to see which cells have not changed state correctly; cycles are then repeated as necessary for those cells which have not yet correctly changed state using a slightly higher voltage each iteration until the cells either have the correct state or until an error is generated (the unit would then typically be marked as “bad”).
An unfortunate side effect of this methodology is that the state change operations can take significant time to complete; for example, write transactions can take ten times longer than read transactions in NAND flash memory, and more than one-thousand times longer than read transactions in NOR flash memory. Attempts to address this problem have usually focused on using plural non-volatile devices, or on dividing up memory space in to what are effectively multiple banks, each with supporting circuitry allowing each bank or device to be independently read. Generally speaking, however, most structures still do not support concurrent processing upon the same basic “bank” served by a single sense array and supporting write circuitry, i.e., subsequent read, erase, write or other transactions must typically be queued until all iterative cycles of a prior operation have fully completed for the block or page in question.
What is needed is a way to mitigate the aforementioned problem, ideally if possible, eliminating the bottleneck entirely by permitting the initiation of read, program or erase operations notwithstanding that a prior program or erase operation is in progress. The present inventions address this need and provide further, related advantages.